Main Page

From Project 54/74
Jump to: navigation, search

What is Project 54/74?

(See also the About page)

This project seeks to document 54xx/74xx-series logic chips and subfamilies by imaging and annotating their dies and tracing out their schematics. These chips usually have no more than 100 transistors, making them easy to understand. They are in the small- or medium-scale integration range. Other series may be represented, but for now we are predominantly concentrating on 54xx and 74xx chips.

The project started on March 4, 2017.

Questions, comments, corrections, and so on can be sent to me at Rob Baruch (robert.c.baruch@gmail.com). See also Contact.

You can also help me by checking out my Patreon page.

It's a Texas Instruments SN5474 flip flop in a metal/glass hermetic package from 1969. SN stood for Semiconductor Network, which was a synonym for Integrated Circuit. The 54 series was introduced by TI in 1964, following on from the original type 504 flip flop (1960), and the digital logic series 51 (1961), 52 (1962), and 53 (1964).

The techniques

See the main article on techniques, or a quick five-minute video tour.

Queue

The queue is a list of chips that have been decapsulated but not yet reverse engineered. Enterprising reverse engineers may want to take these images and try their hand at it. You will need the latest version of Inkscape, and start with opening the Project 54/74 Inkscape template (right click on the link and save link as...). Import the die photo onto the Die Image layer, and start drawing!

Chip
54AS00 TI 8747
5404 TI 7426
7404 TI 8005
74LS08 TI 8022
74S11 SIG 8150
74S175 TI 7939
74HC942 NS 9342

The chips

These are chips and variants that the project has. The variant "x" means standard. If the row is highlighted and there's a link in the Number column, then there is at least one die image available. The link goes to a page showing details about the variants in inventory. That page in turn has links to the individual chip instances as well as to related chips. But why describe that here: pick a chip and explore!

See also: My spreadsheet of chips I have.

See also: List of 7400 series integrated circuits

Terms

  • buffer: Has a higher fan-out than usual.
  • line receiver: Has a lower input load.
  • open collector: Essentially a switch to ground for 0, but high-impedance for 1. Open collector outputs can be wired together to form an AND gate called a wire-AND.
  • Schmitt trigger: Has hysteresis on inputs.

List of chips

Number Function 54xx Inventory 74xx Inventory
00 quad 2-input NAND gate x, AS, S x, F, HC, HCT, LS, S
01 quad 2-input NAND gate, open collector outputs x, LS
02 quad 2-input NOR gate LS, S x, F, HC, HCT, LS, S
03 quad 2-input NAND gate, open collector outputs x, LS
04 hex inverter x, AS x, F, L, LS, S
05 hex inverter, open collector outputs ALS x, LS
06 hex inverter buffer/driver, 30 V open collector outputs x x
07 hex buffer/driver, 30 V open collector outputs x
08 quad 2-input AND gate x, AS x, ALS, AS, F, H, HC, LS, S
09 quad 2-input AND gate, open collector outputs x, LS, S
10 triple 3-input NAND gate x, L x, F, LS, S
11 triple 3-input AND gate x, F, HC, LS, S
12 triple 3-input NAND gate, open collector outputs x x, LS
14 hex Schmitt trigger inverter x x, HCT, LS
16 hex inverter buffer/driver, 15 V open collector outputs x
17 hex buffer/driver, 15 V open collector outputs x
20 dual 4-input NAND gate x x, F, L, LS, S
21 dual 4-input AND gate x, H
22 dual 4-input NAND gate, open collector outputs H
23 expandable dual 4-input NOR gate, strobe x
25 dual 4-input NOR gate x
27 triple 3-input NOR gate x, LS
28 quad 2-input NOR buffer LS x
30 8-input NAND gate x, S x, L, LS
32 quad 2-input OR gate AS x, ALS, F, HC, HCT, LS
33 quad 2-input NOR buffer, open collector outputs LS
37 quad 2-input NAND buffer x, LS x
38 quad 2-input NAND buffer, open collector outputs S x, LS
39 quad 2-input NAND buffer, open collector outputs,
input and output terminals flipped, otherwise functionally identical to 7438
x
40 dual 4-input NAND buffer x
41 BCD to decimal decoder/Nixie tube driver x
42 BCD to decimal decoder x, LS
45 BCD to decimal decoder/driver x x
47 BCD to 7-segment decoder/driver, 15 V open collector outputs x
51 dual 2-wide 2-input AND-OR-invert gate L, LS, S
54 3-2-2-3-input AND-OR-invert gate x
70 AND-gated positive edge triggered J-K flip-flop, asynchronous preset and clear x
72 AND gated J-K master-slave flip-flop, asynchronous preset and clear x
73 dual J-K flip-flop, asynchronous clear x, HC, L, LS
74 dual D positive edge triggered flip-flop, asynchronous preset and clear x, AS x, AS, F, HC, L, LS, S
75 4-bit bistable latch x, HC, LS
76 dual J-K flip-flop, asynchronous preset and clear x, H, HC, LS
83 4-bit binary half adder (no carry in function) x
85 4-bit magnitude comparator S x, LS, S
86 quad 2-input XOR gate x, F, HC, L, LS, S
89 64-bit RAM x, C
90 decade counter (separate divide-by-2 and divide-by-5 sections) x
91 8-bit shift register, serial In, serial out, gated input x
92 divide-by-12 counter (separate divide-by-2 and divide-by-6 sections) x, LS
93 4-bit binary counter (separate divide-by-2 and divide-by-8 sections) x, L, LS
95 4-bit shift register, parallel in, parallel out, serial input x, LS x, C, L
96 5-bit parallel-in/parallel-out shift register, asynchronous preset x
100 dual 4-bit bistable latch x
103 dual J-K negative-edge-triggered flip-flop, clear H
107 dual J-K flip-flop, clear x, LS
109 dual J-Not-K positive-edge-triggered flip-flop, clear and preset LS x, F, LS
112 dual J-K negative-edge-triggered flip-flop, clear and preset HC, LS, S
113 dual J-K negative-edge-triggered flip-flop, preset F
121 monostable multivibrator x
122 retriggerable monostable multivibrator, clear x, LS
123 dual retriggerable monostable multivibrator, clear x, HC, LS
125 quad bus buffer, three-state outputs, negative enable x, HCT, LS
126 quad bus buffer, three-state outputs, positive enable LS
132 quad 2-input NAND Schmitt trigger x, S x, LS, S
134 12-input NAND gate, three-state output S
136 quad 2-input XOR gate, open collector outputs LS
138 3 to 8-line decoder/demultiplexer, inverting outputs AS, F F, HC, HCT, LS
139 dual 2 to 4-line decoder/demultiplexer, inverting outputs F, LS
148 8-line to 3-line priority encoder x, LS
151 8-line to 1-line data selector/multiplexer LS
153 dual 4-line to 1-line data selector/multiplexer, non-inverting outputs AS, F, LS
154 4-line to 16-line decoder/demultiplexer, inverting outputs x
155 dual 2-line to 4-line decoder/demultiplexer, inverting outputs x, LS
157 quad 2-line to 1-line data selector/multiplexer, non-inverting outputs x, F, HC, LS
158 quad 2-line to 1-line data selector/multiplexer, inverting outputs LS, S
161 synchronous presettable 4-bit binary counter, asynchronous clear AS x, F, HC, LS
163 synchronous presettable 4-bit binary counter, synchronous clear x x, F, LS, S
164 8-bit parallel-out serial shift register, asynchronous clear F
165 8-bit serial shift register, parallel load, complementary outputs LS LS
166 parallel-load 8-bit shift register LS, S
169 synchronous presettable 4-bit up/down binary counter F
173 quad D flip-flop, three-state outputs and asynchronous clear LS
174 hex D flip-flop, common asynchronous clear F, LS
175 quad D edge-triggered flip-flop, complementary outputs and asynchronous clear x, ALS, LS, S
181 4-bit arithmetic logic unit and function generator x, LS
182 lookahead carry generator x
189 64-bit (16x4) RAM, inverting three-state outputs LS, S
190 synchronous presettable up/down decade counter LS
191 synchronous presettable up/down binary counter F, LS
192 synchronous presettable up/down decade counter, clear LS
193 synchronous presettable up/down 4-bit binary counter, clear F, LS
194 4-bit bidirectional universal shift register LS
195 4-bit parallel-access shift register LS, S
197 presettable binary counter/latch LS LS
198 8-bit bidirectional universal shift register x
199 8-bit bidirectional universal shift register, J-Not-K serial inputs x
200 256-bit RAM, three-state outputs x
219 64-bit (16x4) RAM, non-inverting three-state outputs F
221 dual monostable multivibrator, Schmitt trigger input LS
238 3-of-8 decoder/demultiplexer, active high outputs HC
240 octal buffer, inverting three-state outputs AS LS, S
241 octal buffer, non-inverting three-state outputs LS, S
244 octal buffer, non-inverting three-state outputs LS AS, F, HC, HCT, HCTLS, LS, S
245 octal bus transceiver, non-inverting three-state outputs F, HCTLS, LS
248 BCD to 7-segment decoder/driver, Internal Pull-up outputs x
257 quad 2-line to 1-line data selector/multiplexer, non-inverting three-state outputs F, LS, S
258 quad 2-line to 1-line data selector/multiplexer, inverting three-state outputs F, LS
259 8-bit addressable latch LS LS
260 dual 5-input NOR gate LS
269 8-bit bidirectional binary counter F
273 8-bit register, asynchronous clear F, LS, S
280 9-bit odd/even parity bit generator/checker LS, S
283 4-bit binary full adder (has carry in function) LS F, LS
290 decade counter (separate divide-by-2 and divide-by-5 sections) LS
293 4-bit binary counter (separate divide-by-2 and divide-by-8 sections) LS
298 quad 2-input multiplexer, storage LS
299 8-bit bidirectional universal shift/storage register, three-state outputs LS
322 8-bit shift register, sign extend, three-state outputs F
323 8-bit bidirectional universal shift/storage register, three-state outputs LS
324 voltage-controlled oscillator (or crystal controlled) LS
350 4-bit shifter, three-state outputs F
365 hex buffer, non-inverting three-state outputs LS
366 hex buffer, inverting three-state outputs LS
367 hex buffer, non-inverting three-state outputs x, LS
368 hex buffer, inverting three-state outputs x, LS
373 octal transparent latch, three-state outputs LS F, LS, S
374 octal register, three-state outputs AS F, HC, HCT, HCTLS, LS, S
375 quad bistable latch LS
377 8-bit register, clock enable LS HC, LS
381 4-bit arithmetic logic unit/function generator, generate and propagate outputs F
382 4-bit arithmetic logic unit/function generator, ripple carry and overflow outputs F
390 dual 4-bit decade counter LS
393 dual 4-bit binary counter x LS
398 quad 2-input multiplexers, storage and complementary outputs F
399 quad 2-input multiplexer, storage LS
453 quad 4-to-1 multiplexer HCT
460 bus transfer switch LS
521 8-bit comparator, inverting totem-pole output F
524 8-bit registered comparator F
534 octal register, inverting three-state outputs LS
538 1 of 8 decoder, three-state outputs F
543 octal registered transceiver, three-state outputs F
569 binary up/down counter, three-state outputs F
592 8-bit binary counter, input registers LS
624 voltage-controlled oscillator, enable control, range control, two-phase outputs LS
645 octal bus transceiver ALS
646 octal bus transceiver/latch/multiplexer, non-inverting three-state outputs HCT
670 4 by 4 register file, three-state outputs LS
867 synchronous 8-bit up/down counter, asynchronous clear AS
942 300 baud modem HC
3040 dual 4-input NAND 30Ω line driver F