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What is Project 54/74?

(See also the About page)

This project seeks to document 54xx/74xx-series logic chips and subfamilies by imaging and annotating their dies and tracing out their schematics. These chips usually have no more than 100 transistors, making them easy to understand. They are in the small- or medium-scale integration range. Other series may be represented, but for now we are predominantly concentrating on 54xx and 74xx chips.

The project started on March 4, 2017.

Questions, comments, corrections, and so on can be sent to me at Rob Baruch (robert.c.baruch@gmail.com). See also Contact.

You can also help me by checking out my Patreon page.

It's a Texas Instruments SN5474 flip flop in a metal/glass hermetic package from 1969. SN stood for Semiconductor Network, which was a synonym for Integrated Circuit. The 54 series was introduced by TI in 1964, following on from the original type 504 flip flop (1960), and the digital logic series 51 (1961), 52 (1962), and 53 (1964).

The techniques

See the main article on techniques, or a quick five-minute video tour.

Databooks

Besides technical information about each chip, databooks often have introductory sections giving circuit details and characteristics, design recommendations, and definitions. It is worth the designer's time to go through each databook's introduction. See the main article on Databooks.

Queue

The queue is a list of chips that have been decapsulated but not yet reverse engineered. Enterprising reverse engineers may want to take these images and try their hand at it. You will need the latest version of Inkscape, and start with opening the Project 54/74 Inkscape template (right click on the link and save link as...). Import the die photo onto the Die Image layer, and start drawing!

The chips

These are chips and variants that the project has. The variant "x" means standard. If the row is highlighted and there's a link in the Number column, then there is at least one die image available. The link goes to a page showing details about the variants in inventory. That page in turn has links to the individual chip instances as well as to related chips. But why describe that here: pick a chip and explore!

See also: My spreadsheet of chips I have.

See also: List of 7400 series integrated circuits

Terms

  • buffer: Has a higher fan-out than usual.
  • line receiver: Has a lower input load.
  • open collector: Essentially a switch to ground for 0, but high-impedance for 1. Open collector outputs can be wired together to form an AND gate called a wire-AND.
  • Schmitt trigger: Has hysteresis on inputs.

List of chips

Number Function 54xx Inventory 74xx Inventory
00 quad 2-input NAND gate x, AS, HC, S x, ACT, ALS, AS, C, F, H, HC, HCT, L, LS, S
01 quad 2-input NAND gate, open collector outputs x, AHCT, ALS, H, LS
02 quad 2-input NOR gate x, LS, S x, AC, ALS, AS, C, F, HC, HCT, HCTLS, L, LS, S
03 quad 2-input NAND gate, open collector outputs x, ALS, HC, LS, S
04 hex inverter x, AS x, AC, ALS, AS, F, H, HCT, L, LS, S
05 hex inverter, open collector outputs ALS x, AC, ALS, HC, HCTLS, LS, S
06 hex inverter buffer/driver, 30 V open collector outputs x x
07 hex buffer/driver, 30 V open collector outputs x
08 quad 2-input AND gate x, AS x, ACT, ALS, AS, C, F, H, HC, HCT, HCTLS, LS, S
09 quad 2-input AND gate, open collector outputs x, LS, S
10 triple 3-input NAND gate x, L x, ALS, AS, C, F, H, HC, HCT, L, LS, S
11 triple 3-input AND gate x, ALS, F, H, HC, HCT, LS, S
12 triple 3-input NAND gate, open collector outputs x x, ALS, HCTLS, LS
13 dual Schmitt trigger 4-input NAND gate x, LS
14 hex Schmitt trigger inverter x x, HC, HCT, LS
15 triple 3-input AND gate, open collector outputs LS, S
16 hex inverter buffer/driver, 15 V open collector outputs x
17 hex buffer/driver, 15 V open collector outputs x
20 dual 4-input NAND gate x x, AS, C, F, H, HC, L, LS, S
21 dual 4-input AND gate x, ALS, AS, H, HCT, L, LS
22 dual 4-input NAND gate, open collector outputs ALS x, H, LS, S
23 expandable dual 4-input NOR gate, strobe x
25 dual 4-input NOR gate x
26 quad 2-input NAND gate, 15 V open collector outputs x, LS
27 triple 3-input NOR gate x x, ALS, AS, HC, HCT, LS
28 quad 2-input NOR buffer LS x, LS
30 8-input NAND gate x, S x, C, H, HC, HCT, L, LS, S
31 hex delay elements LS
32 quad 2-input OR gate AS, HC x, AC, ACT, ALS, AS, F, HC, HCT, HCTLS, LS, S
33 quad 2-input NOR buffer, open collector outputs x x, LS
37 quad 2-input NAND buffer x, ALS, LS x, LS, S
38 quad 2-input NAND buffer, open collector outputs x, S x, ALS, F, LS, S
39 quad 2-input NAND buffer, open collector outputs,
input and output terminals flipped, otherwise functionally identical to 7438
x
40 dual 4-input NAND buffer x x, LS, S
41 BCD to decimal decoder/Nixie tube driver x
42 BCD to decimal decoder LS x, C, LS
44 excess-3-Gray code to decimal decoder x, HCT
45 BCD to decimal decoder/driver x x
46 BCD to 7-segment display decoder/driver, 30 V open collector outputs x
47 BCD to 7-segment decoder/driver, 15 V open collector outputs x
50 dual 2-wide 2-input AND-OR-invert gate (one gate expandable) x, H
51 dual 2-wide 2-input AND-OR-invert gate x, F, H, HC, HCT, L, LS, S
52 expandable 4-wide 2-input AND-OR gate H
53 expandable 4-wide 2-input AND-OR-invert gate x, H
54 3-2-2-3-input AND-OR-invert gate x, LS
55 2-wide 4-input AND-OR-invert gate (74H version is expandable) LS
60 dual 4-input expander x
62 3-2-2-3-input AND-OR expander H
64 4-2-3-2-input AND-OR-invert gate S
65 4-2-3-2 input AND-OR-invert gate, open collector output S
70 AND-gated positive edge triggered J-K flip-flop, asynchronous preset and clear x
72 AND gated J-K master-slave flip-flop, asynchronous preset and clear x
73 dual J-K flip-flop, asynchronous clear x x, H, HC, HCT, L, LS
74 dual D positive edge triggered flip-flop, asynchronous preset and clear x, AS, HC x, AC, ALS, AS, C, F, HC, HCT, L, LS, S
75 4-bit bistable latch x, HC, L, LS
76 dual J-K flip-flop, asynchronous preset and clear C x, C, H, HC, LS
78 dual positive pulse triggered J-K flip-flop, preset, common clock and common clear H
LS78 dual negative edge triggered J-K flip-flop, preset, common clock and common clear LS
80 gated full adder x
81 16-bit RAM x
83 4-bit binary half adder (no carry in function) x
85 4-bit magnitude comparator S x, LS, S
86 quad 2-input XOR gate x, F, HC, HCT, L, LS, S
89 64-bit RAM x, C
90 decade counter (separate divide-by-2 and divide-by-5 sections) x
91 8-bit shift register, serial In, serial out, gated input x
92 divide-by-12 counter (separate divide-by-2 and divide-by-6 sections) x, LS
93 4-bit binary counter (separate divide-by-2 and divide-by-8 sections) LS x, L, LS
95 4-bit shift register, parallel in, parallel out, serial input x, LS x, C, L
96 5-bit parallel-in/parallel-out shift register, asynchronous preset x
100 dual 4-bit bistable latch x
103 dual J-K negative-edge-triggered flip-flop, clear H
107 dual J-K flip-flop, clear x x, AHCT, HCT, LS
109 dual J-Not-K positive-edge-triggered flip-flop, clear and preset LS x, AHCT, F, LS, S
112 dual J-K negative-edge-triggered flip-flop, clear and preset HC, HCT, LS, S
113 dual J-K negative-edge-triggered flip-flop, preset ALS, F, S
114 dual J-K negative-edge-triggered flip-flop, preset, common clock and clear ALS, LS, S
121 monostable multivibrator x
122 retriggerable monostable multivibrator, clear x, LS
123 dual retriggerable monostable multivibrator, clear x, HC, HCT, LS
124 dual voltage-controlled oscillator S
125 quad bus buffer, three-state outputs, negative enable x, HCT, LS
126 quad bus buffer, three-state outputs, positive enable x, LS
132 quad 2-input NAND Schmitt trigger x, S x, F, LS, S
133 13-input NAND gate S
134 12-input NAND gate, three-state output S
136 quad 2-input XOR gate, open collector outputs LS
138 3 to 8-line decoder/demultiplexer, inverting outputs AS, F AHCT, F, HC, HCT, LS, S
139 dual 2 to 4-line decoder/demultiplexer, inverting outputs AHCT, F, LS
140 dual 4-input NAND line driver S
141 BCD to decimal decoder/driver for cold-cathode indicator/Nixie tube x
142 decade counter/latch/decoder/driver for Nixie tubes x
143 decade counter/latch/decoder/7-segment driver, 15 mA constant current x
144 decade counter/latch/decoder/7-segment driver, 15 V open collector outputs x
145 BCD to decimal decoder/driver x, HCT, LS
148 8-line to 3-line priority encoder x, LS
149 8-line to 8-line priority encoder HCT
150 16-line to 1-line data selector/multiplexer x
151 8-line to 1-line data selector/multiplexer HCT, LS, S
153 dual 4-line to 1-line data selector/multiplexer, non-inverting outputs ACT, AS, F, LS
154 4-line to 16-line decoder/demultiplexer, inverting outputs x
155 dual 2-line to 4-line decoder/demultiplexer, inverting outputs x, AHCT, LS
156 dual 2-line to 4-line decoder/demultiplexer, open collector inverting outputs x, LS
157 quad 2-line to 1-line data selector/multiplexer, non-inverting outputs x, F, HC, HCT, LS, S
158 quad 2-line to 1-line data selector/multiplexer, inverting outputs HCT, LS, S
160 synchronous presettable 4-bit decade counter, asynchronous clear HCT
161 synchronous presettable 4-bit binary counter, asynchronous clear AS x, F, HC, LS, S
162 synchronous presettable 4-bit decade counter, synchronous clear HCT, S
163 synchronous presettable 4-bit binary counter, synchronous clear x x, F, HCT, LS, S
164 8-bit parallel-out serial shift register, asynchronous clear F, HCT
165 8-bit serial shift register, parallel load, complementary outputs LS x, LS
166 parallel-load 8-bit shift register LS, S
169 synchronous presettable 4-bit up/down binary counter F, S
173 quad D flip-flop, three-state outputs and asynchronous clear HCT, LS
174 hex D flip-flop, common asynchronous clear F, HC, LS, S
175 quad D edge-triggered flip-flop, complementary outputs and asynchronous clear x, ALS, HC, HCT, LS, S
177 presettable binary counter/latch x
181 4-bit arithmetic logic unit and function generator x, LS, S
182 lookahead carry generator x, S
189 64-bit (16x4) RAM, inverting three-state outputs LS, S
190 synchronous presettable up/down decade counter LS
191 synchronous presettable up/down binary counter F, HC, LS
192 synchronous presettable up/down decade counter, clear LS
193 synchronous presettable up/down 4-bit binary counter, clear x, F, LS
194 4-bit bidirectional universal shift register x LS, S
195 4-bit parallel-access shift register LS, S
197 presettable binary counter/latch LS x, LS
198 8-bit bidirectional universal shift register x
199 8-bit bidirectional universal shift register, J-Not-K serial inputs x
200 256-bit RAM, three-state outputs x, S
219 64-bit (16x4) RAM, non-inverting three-state outputs F
221 dual monostable multivibrator, Schmitt trigger input LS
225 asynchronous 16x5 FIFO memory S
237 3-of-8 decoder/demultiplexer, address latch, active high outputs HCT
238 3-of-8 decoder/demultiplexer, active high outputs HC
240 octal buffer, inverting three-state outputs AS C, HCT, LS, S
241 octal buffer, non-inverting three-state outputs HCT, LS, S
242 quad bus transceiver, inverting three-state outputs HCT, LS
243 quad bus transceiver, non-inverting three-state outputs LS
244 octal buffer, non-inverting three-state outputs LVTH, LS AHCT, AS, F, HC, HCT, HCTLS, LS, S
245 octal bus transceiver, non-inverting three-state outputs ALS, F, HCT, HCTLS, LS
248 BCD to 7-segment decoder/driver, Internal Pull-up outputs x
251 8-line to 1-line data selector/multiplexer, complementary three-state outputs HCT, LS, S
253 dual 4-line to 1-line data selector/multiplexer, three-state outputs LS LS, S
257 quad 2-line to 1-line data selector/multiplexer, non-inverting three-state outputs F, LS, S
258 quad 2-line to 1-line data selector/multiplexer, inverting three-state outputs F, LS
259 8-bit addressable latch LS HCT, LS
260 dual 5-input NOR gate LS, S
266 quad 2-input XNOR gate, open collector outputs HCT
269 8-bit bidirectional binary counter F
273 8-bit register, asynchronous clear x, F, HC, HCT, LS, S
274 4-bit by 4-bit binary multiplier S
280 9-bit odd/even parity bit generator/checker LS, S
283 4-bit binary full adder (has carry in function) LS F, LS
289 64-bit (16x4) RAM, open collector outputs S
290 decade counter (separate divide-by-2 and divide-by-5 sections) LS
293 4-bit binary counter (separate divide-by-2 and divide-by-8 sections) LS
298 quad 2-input multiplexer, storage HCT, LS
299 8-bit bidirectional universal shift/storage register, three-state outputs LS, S
301 256-bit (256x1) RAM, open collector output S
322 8-bit shift register, sign extend, three-state outputs F
323 8-bit bidirectional universal shift/storage register, three-state outputs LS
324 voltage-controlled oscillator (or crystal controlled) LS
350 4-bit shifter, three-state outputs F
352 dual 4-line to 1-line data selectors/multiplexers, inverting outputs LS
353 dual 4-line to 1-line data selectors/multiplexers, inverting three-state outputs LS
354 8 to 1-line data selector/multiplexer, transparent latch, three-state outputs LS
356 8 to 1-line data selector/multiplexer, edge-triggered register, three-state outputs HCT
362 four-phase clock generator/driver LS
364 8-bit D-type edge-triggered register, three-state outputs LS
365 hex buffer, non-inverting three-state outputs LS HCT
366 hex buffer, inverting three-state outputs x, HC, HCT, LS
367 hex buffer, non-inverting three-state outputs x, AHCT, LS
368 hex buffer, inverting three-state outputs x, HCT, LS
373 octal transparent latch, three-state outputs LS AHCT, F, HCT, LS, S
374 octal register, three-state outputs AS ACT, AHCT, F, HC, HCT, HCTLS, LS, S
375 quad bistable latch HCT, LS
376 quad J-Not-K flip-flop, common clock and common clear x
377 8-bit register, clock enable LS HC, HCT, LS
378 6-bit register, clock enable LS
381 4-bit arithmetic logic unit/function generator, generate and propagate outputs F
382 4-bit arithmetic logic unit/function generator, ripple carry and overflow outputs F
390 dual 4-bit decade counter LS
393 dual 4-bit binary counter x AHCT, HC, LS
398 quad 2-input multiplexers, storage and complementary outputs F
399 quad 2-input multiplexer, storage LS
408 8-bit parity tree S
445 BCD-to-decimal decoders/drivers LS
453 quad 4-to-1 multiplexer HCT
460 bus transfer switch LS
475 PROM, three-state outputs S
491 10-bit binary up/down counter, limited preset and three-state outputs LS
521 8-bit comparator, inverting totem-pole output F
524 8-bit registered comparator F
534 octal register, inverting three-state outputs HCT, LS
538 1 of 8 decoder, three-state outputs F
540 inverting octal buffer, three-state outputs HCT
541 non-inverting octal buffer, three-state outputs AHCT, LS
543 octal registered transceiver, three-state outputs F
563 8-bit D-type transparent latch, inverting three-state outputs AHCT
564 8-bit D-type edge-triggered register, inverting three-state outputs AHCT
569 binary up/down counter, three-state outputs F
573 octal D-type transparent latch, three-state outputs AHCT, ALS
574 octal D-type edge-triggered flip-flop, three-state outputs HCT
592 8-bit binary counter, input registers LS
595 8-bit shift registers, output latches, three-state parallel outputs HC
604 octal 2-input multiplexer, latch, high-speed, three-state outputs LS
624 voltage-controlled oscillator, enable control, range control, two-phase outputs LS
629 dual voltage-controlled oscillator, enable control, range control LS
640 octal bus transceiver, inverting three-state outputs LS LS
641 octal bus transceiver, non-inverting open collector outputs ALS
643 octal bus transceiver, mix of inverting and non-inverting three-state outputs AHCT
645 octal bus transceiver ALS
646 octal bus transceiver/latch/multiplexer, non-inverting three-state outputs AHCT, HCT
648 octal bus transceiver/latch/multiplexer, inverting three-state outputs AHCT
670 4 by 4 register file, three-state outputs LS
674 16-bit parallel-in serial-out shift register, three-state outputs LS
682 8-bit magnitude comparator LS
683 8-bit magnitude comparator, open collector outputs LS
688 8-bit equality comparator LS HC
867 synchronous 8-bit up/down counter, asynchronous clear AS
942 300 baud modem HC
3040 dual 4-input NAND 30Ω line driver F
4002 dual 4-input NOR gate HCT

Other chips

Category
CMOS
RAM